edaa outstanding dissertation award

July 16, 2019 -- In recognition of the importance of university research to the advancement of design, automation and test, and to encourage young researchers to work in the field, EDAA has established an award for outstanding Ph.D. dissertations in 4 categories:

Topic 1 – New directions in embedded software design and optimization for embedded, cyber-physical , secure and learning systems.

Topic 2 – New directions in system-on-chip platforms co-design, novel architectures and system-level architectures, design flows, management.

Topic 3 – New directions in logic, physical design and CAD for analog/mixed-signal, nano-scale and emerging technologies.

Topic 4 – New directions in safety, reliability, security-aware hardware design, validation and test

In each category, one award can be given. Each award consists of a 1000 € prize and certificate. The awards will be presented at the DATE 2020 conference, where the awardees need to be present.

• Eligible are all Ph.D. dissertations which have been defended in the last 2 years before the submission deadline. The total reporting time should not be more than 5 years since the starting of the PhD that should clearly be stated in the applicant CV.
• Nominations shall be submitted electronically and shall contain:
• an indication of the category (one only);
• an extended statement (PDF format) explaining the outstanding contributions of the thesis;
• the PhD Thesis, preferably in English (PDF format); A thesis which is written in a language other than English must be accompanied by sufficient published material in English so that the jury can judge the contributions and quality of the PhD work,
• a CV and a list of related publications.
• Nominations shall be supported by at least 3 reference letters of experts in the respective fields, with at least one reference letter from a different university. Reference letters need to be submitted to the website and must carry the name of the candidate in the filename.
• Awardees must be present at DATE 2020 to receive the Award.
• SPRINGER will publish these awarded dissertations in the EDAA Outstanding Monographs series.

Deadline  for nominations is November 1 st , 2019 at midnight (AOE).

The nominations must be submitted electronically, exclusively in PDF format, through the following URL address:  https://www.edaa.com/EDAA-Award Contact:

Lorena Anghel Grenoble INP Institute of Engineering, and EDAA Vice-Chair Email Contact

Purdue alumnus receives EDAA Outstanding Dissertation Award - Elmore Family School of Electrical and Computer Engineering - Purdue University

Purdue alumnus receives EDAA Outstanding Dissertation Award

A Purdue ECE alumnus has been selected to receive the EDAA Outstanding Dissertation Award 2019 in recognition research done as a PhD student at Purdue. Ahmedullah Aziz received his PhD ECE in 2019. His dissertation was entitled “Device-Circuit Co-design Employing Phase Transition Materials for Low Power Electronics.” This is the first time a Purdue grad has received this international recognition, which is given by the European Design and Automation Association (EDAA) annually.

The EDAA established the award in 2003 to recognize the importance of university research to the advancement of design, automation and test, and to encourage young researchers to work in the field. Four award categories were considered for 2019. Aziz’s award is in the category of “New Directions in logic, physical design and CAD for analog/mixed-signal, nano-scale and emerging technologies.”

Aziz’s says he is deeply honored to receive this recognition.

“It will be a significant milestone in my career and will encourage me in my future endeavors,” he says. “I am grateful to my Ph.D. supervisor, Dr. Sumeet Gupta, doctoral committee members, academic mentors, and my family for their relentless support and encouragement.”

Aziz also received the Outstanding Graduate Student Research Award from Purdue’s College of Engineering in 2019. His Ph.D. research portfolio comprised of a diverse and broad domain of emerging electronics. Aziz worked on device-circuit co-design with CMOS and post-CMOS technologies to overcome daunting challenges in the concurrent semiconductor industry. He explored and utilized unique characteristics of complex materials like correlated oxides, ferroelectrics, and 2D transition metal di-chalcogenides to design novel devices and circuits for the next-generation processors and digital data storage.

Aziz is currently a tenure-track assistant professor in the Department of Electrical Engineering and Computer Science (EECS) at the University of Tennessee, Knoxville. 

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Dr. Mishra wins 2004 EDAA Outstanding Dissertation Award

January 25, 2005 @ 1:00 pm pst.

Dr. Prabhat Mishra  won the EDAA outstanding dissertation award for the topic “New Directions in Embedded System Design Automation.” His paper is titled, “Specification-Driven Validation of Programmable Embedded Systems.”

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Bei Yu Receives EDAA Outstanding Dissertation Award

Dr. Bei Yu (Ph.D. 2014) has been selected to receive the 2014 Outstanding Dissertation Award in the area of "New directions in physical design, design for manufacturing and CAD for analogue circuits and MEMS" from the European Design and Automation Association (EDAA) for his dissertation "Design for Manufacturing with Advanced Lithography". As one of the most prestigious Ph.D. dissertation awards in the field of Electronic Design Automation (EDA), this award will be presented in March at the DATE 2015 conference in Grenoble, France. The award includes a monetary prize and an offer to publish the dissertation in the Springer EDAA Outstanding Monographs series.

Dr. Yu's dissertation offers novel design technology co-optimization solutions in advanced lithography across multiple levels. On the mask optimization level, the dissertation develops the first systematic framework on triple patterning layout decomposition, where a set of graph algorithms and mathematical programming techniques are proposed. The dissertation also develops novel L-shaped based layout fracturing algorithms for electron beam lithography (EBL). On the physical design level, the dissertation presents a coherent framework on standard cell compliance and detailed placement to enable triple patterning friendly design. On the system optimization level, it proposes effective overlapping aware stencil planning for the multi-column cell (MCC) system.

Dr. Yu is currently a postdoctoral scholar at the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include design for manufacturing with advanced lithography, cyber-physical systems, hardware security, machine learning and combinatorial algorithms with applications in VLSI CAD. He has received a number of awards, including Best Paper Awards at ICCAD'13 and ASPDAC'12, Best Paper Award Nominations at DAC'14, ASPDAC'13, and ICCAD’11,  ACM Student Research Contest Silver Metal at ICCAD 2013, 2014 Chinese Government Award for Outstanding Students Abroad, 2013 SPIE Education Scholarship, 2012 IBM Scholarship, and ICCAD CAD Contest Awards in 2012 and 2013.

Dr. Bei Yu's dissertation advisor is Professor David Z. Pan. More about Bei Yu  http://www.cerc.utexas.edu/~bei/  

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David Papa receives EDAA Outstanding Dissertation Award

Dr. David Papa (CSE Ph.D. 2010) has been selected to receive the 2010 Outstanding Dissertation Award in the area of “New directions in physical design, design for manufacturing and CAD for analogue circuits and MEMS” from the European Design and Automation Association (EDAA) for  his dissertation , “Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits,”  which he defended at the University of Michigan. The award will be presented in March at the  DATE 2011  conference in Grenoble, France. This award is among the most prestigious awards for Ph.D. dissertations in the field of Electronic Design Automation (EDA).

Dr. Papa’s dissertation offers solutions to chip optimization problems collectively known as physical synthesis. One of the challenges it addresses is a disconnect between global optimizations that deal with entire circuits and greedy local optimizations that apply to single gates and wires. Global optimizations suffer from inaccurate models of circuit delay and sometimes make things worse. Local optimizations are safe, but lack the scope to contribute significant improvement.

The research reported in the dissertation enhances physical synthesis by improving the efficiency and accuracy of circuit delay models used for global optimizations, extending the scope of local optimizations, and creating hybrid optimizations that deal with several degrees of freedom at the same time. The dissertation develops a suite of interrelated multi-objective optimizations that considerably improve commercial software for chip optimization. These techniques are now adopted at IBM within standard chip design methodologies.

Upon concluding his doctoral studies at the University of Michigan, Dr. Papa has continued his physical synthesis research in the Design Productivity Group at IBM Research in Austin, TX.

Dr. Papa’s dissertation advisor was Professor  Igor Markov .

Award Announcement by EDAA  (pdf)

EDAA is an open non-profit association, aiming at educational, scientific and technical purposes for the benefit of the international electronics design and design automation community. As part of this, EDAA annually sponsors several awards and promotes a series of high-quality technical international conferences (e.g. DATE) and workshops across Europe.

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Dr. Xiao Liu Won the EDAA Outstanding Dissertation Award 2012

Congratulations to Dr. Xiao LIU, a PhD student supervised by Prof. Xu Qiang won the European Design and Automation Association (EDAA) Outstanding Dissertation Award 2012. His thesis titled “Trace-Based Post-Silicon Validation for VLSI Circuits” won the award in the area of “New directions in circuit and system test”.

Abstract: The ever-increasing design complexity of modern circuits challenges our ability to verify their correctness. Therefore, various errors are more likely to escape the pre-silicon verification process and to manifest themselves after design tape-out. To address this problem, effective post-silicon validation is essential for eliminating design bugs before integrated circuit (IC) products shipped to customers. In the debug process, it becomes increasingly popular to insert design-for-debug (DfD) structures into the original design to facilitate real-time debug without intervening the circuits’ normal operation. For this trace-based post-silicon validation technique, the key question is how to conduct signal tracing effectively to achieve sufficient observability and controllability during the debug process with low-cost DfD structures. However, in today’s VLSI design flow, this is unfortunately conducted in a manual fashion based on designers’ own experience, which cannot guarantee debug quality.?

To tackle this problem, we propose a set of automatic tracing solutions as well as innovative DfD designs in this thesis. First, we develop a novel trace signal selection technique to maximize the visibility on debugging functional design errors. To strengthen the capability for tackling these errors, we sequentially introduce a multiplexed signal tracing strategy with a trace signal grouping algorithm for maximizing the probability of catching the propagated evidences from functional design errors. Then, to effectively localize speedpath-related electrical errors, we propose an innovative trace signal selection solution as well as a trace qualification technique. On the other hand, we introduce several low-cost interconnection fabrics to effectively transfer trace data in post-silicon validation. We first propose to reuse the existing test channel for real-time trace data transfer, so that the routing cost of debug hardware is dramatically reduced. The method is further improved to avoid data corruption in multi-core debug. We then develop a novel interconnection fabric design and optimization technique, by combining multiplexor network and non-blocking network, to achieve high debug flexibility with minimized hardware cost. Moreover, we introduce a hybrid trace interconnection fabric that is able to tolerate unknown values in golden vectors, at the cost of little extra DfD overhead. With the fabric, we develop a systematic signal tracing procedure to automatically localize erroneous signals with just a few debug runs. Our empirical evaluation shows that the solutions presented in this thesis can greatly improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices.